EQ Wave v1 Series: Detailed Engineering Changes

Version History - Engineering Details

v1.1 (2024) Engineering Changes

Safety Improvements

• Dual High-Voltage Resistor Divider: Added second high-voltage resistor in series for UL fault tolerance
  • Provides redundancy in case of resistor failure
  • Maintains measurement accuracy while improving safety compliance

Timing and Synchronization

• Timing-Optimized GNSS Receiver: Added precision timing mode GNSS for sub-microsecond time synchronization
  • Enables precise timestamp correlation across multiple sensors
  • Critical for power quality event analysis and grid monitoring applications

Analog Front-End Enhancements

• Improved signal conditioning design
• Enhanced noise performance
• Better thermal stability

v1.2 (2025) Engineering Changes

Power Supply Redesign

• Voltage Divider Upgrade:

  • Component rating: 700V resistors (upgraded from 613V)
  • Higher impedance design for reduced power consumption
  • Ratio changed: 2.5 MΩ : 4.99 kΩ → 4 MΩ : 7.5 kΩ
  • VDIV constant: 1335.833333 (firmware calculation)

• Backup Power System:

  • Added supercapacitor backup power supply
  • Provides ~8 seconds of operation during power interruption
  • BACKUP signal added for firmware monitoring

• PS1 Protection:

  • Added Schottky diode for overvoltage protection
  • Improved thermal management
  • Better surge protection

PCB Layout Improvements

• Impedance Optimization:

  • Reduced impedance loops by tightening vias into pads
  • Improved overall routing and component placement
  • Better signal integrity for high-frequency signals

• Manufacturing Quality:

  • Improved solder mask placement and quality
  • Enhanced font readability and logo placement
  • UL marking moved to back side only for cleaner front appearance

GNSS Subsystem Improvements

• Antenna Performance:

  • Added ground plane under GNSS antenna
  • Direct SMA connector (replaced U.FL pigtail)
  • Improved RF performance and reliability

• Firmware Interface Changes:

  • GNSS UART: UART1 → UART3
  • Pin reassignments: See “Pin Configuration Changes” section below
  • PWR_EN: P0[23] → P1[31]
  • BACKUP signal: New pin P0[23] for backup power monitoring

Analog Signal Conditioning Enhancements

• Anti-Aliasing Filters:

  • Added filters just before ADE9430 for all voltage and current channels
  • Improved frequency response and reduced noise

• RF Interference Mitigation:

  • Added separate early-stage RF shunts for all channels
  • Better isolation between voltage and current measurement paths

• Component Placement Optimization:

  • Moved differential filter resistors close to drivers
  • Placed filter capacitors close to receivers
  • Optimized for signal integrity and noise reduction

Ethernet PHY Improvements

• Thermal Management:

  • Increased PHY bias resistors to 0603 package size
  • Better thermal margin and reliability
  • Resistor values now match TI application note guidance more closely

• Interface Optimization:

  • Removed unnecessary AC coupling capacitors between POF transceiver and PHY
  • Simplified signal path for better reliability
  • Increased LED drive resistors to prevent component burnout

Power Distribution

• Current Measurement Power:
  • Added continuous -4.77V plane under current instrumentation amplifiers
  • Improved power supply noise and stability for analog circuits

Component Selection

• Cost Optimization:

  • Better resistor series selection for reduced cost
  • Fewer required manufacturers for simplified sourcing
  • Maintained or improved electrical performance

• microSD Interface:

  • Replaced obsolete TVS diode with current production equivalent
  • Maintained protection performance

Design Process Improvements

• Manufacturing Integration:

  • Improved process for generating MacroFab production files
  • Better design rule checking and manufacturability

• Documentation Quality:

  • Cleaned up schematic formatting and organization
  • Improved readability and maintenance

Firmware Development Impact

Pin Configuration Changes (v1.2)

Developers updating firmware from v1.1 to v1.2 must account for:

// v1.1 → v1.2 Pin Changes

// GNSS UART Migration (UART1 → UART3):
//   TXD: P2[0] (U1_TXD) → P0[26] (U3_TXD)
//   RXD: P2[1] (U1_RXD) → P0[25] (U3_RXD)

// GNSS Control Pins:
//   BOOT_SEL: P3[26] → P0[28]
//   1PPS:     P0[28] → P0[27]
//   1PPS2:    P0[27] → P3[26]

// Power Management:
//   PWR_EN:   P0[23] → P1[31]
//   BACKUP:   (new) P0[23] - LTC3110 backup power status (active low, open drain)

New Capabilities (v1.2)

• Backup Power Monitoring: Firmware can now monitor backup power status
• Enhanced Power Management: Better control over power states
• Improved GNSS Integration: Direct antenna connection for better performance

Testing and Validation

v1.1 Validation Focus

• UL fault tolerance testing with dual resistor configuration
• Safety compliance verification
• Long-term reliability testing

v1.2 Validation Requirements

• Backup power duration and reliability testing
• Enhanced voltage range validation (600V systems)
• GNSS performance validation with new antenna design
• EMI compliance testing with improved grounding
• Thermal testing with new component placements

Hardware Features Present Across v1.x

Expansion Interfaces (Not Yet Supported in Firmware)

microSD Card Interface

• Hardware Status: Present on all v1.x revisions
• Firmware Status: Not yet implemented
• Planned Use: Local data logging, configuration storage, offline analysis
• Technical Details:
  • Standard SPI interface
  • TVS protection (updated component in v1.2)
  • 3.3V operation

GNSS Receiver (Optional)

• Hardware Status: DNP’d (Do Not Populate) by default
• Installation: Can be field-installed as castellated component
• Firmware Status: Basic support in v1.1+, full integration planned
• Component Options:
  • SkyTraq PX1100T (precision timing mode)
  • SkyTraq PX1125T (enhanced performance)
• Applications: Sub-microsecond time synchronization for multi-sensor deployments

Current Network Services

Dual-Port Architecture

Current firmware implements concurrent data services:

// Network Service Ports (current implementation)
#define CPOW_PORT 1534    // Continuous point-on-wave data
#define PMON_PORT 1535    // Power monitoring metrics
#define CONSOLE_PORT 1536 // Debug console (debug builds only)
#define SMON_PORT 1537    // System monitoring (debug builds only)

Data Stream Characteristics

• PMon Service (Port 1535):

  • Aggregated power quality metrics
  • 10/12 cycle update rate
  • JSON or binary format options
  • Low bandwidth (~1–10 kbps)

• CPOW Service (Port 1534):

  • Raw waveform data streams
  • 32 kHz × 7 channels × 24-bit
  • ~5.33 Mbps sustained data rate
  • Custom binary protocol for efficiency

Firmware Roadmap

Immediate Next Release: Zenoh Integration

Core Zenoh Features

• Remote Configuration: Dynamic parameter updates without firmware flash
• EEPROM Storage: Persistent settings storage replacing hard-flashed configuration
• Distributed Architecture: Integration with larger sensor networks
• Service Discovery: Automatic sensor detection and capability advertisement

Implementation Details

// Planned EEPROM Configuration Structure
typedef struct {
    uint32_t magic;           // Configuration validity marker
    uint16_t version;         // Configuration format version
    sensor_config_t sensor;   // Sampling rates, gains, filters
    network_config_t network; // IP, ports, Zenoh settings
    uint32_t checksum;        // Configuration integrity check
} eeprom_config_t;

Benefits Over Current Hard-Flash Configuration

• Field-configurable without firmware updates
• Multiple configuration profiles
• Remote sensor management
• Reduced deployment complexity

Medium-Term Firmware Features

• GNSS Integration: Full support for optional timing receiver
• Enhanced Diagnostics: Self-test and calibration verification
• Modbus TCP: Industrial protocol support for legacy system integration
• PTP Support: IEEE 1588 precision time protocol

v1.x Architecture Limitations

LPC4078 MCU Constraints

• Flash Memory: 512KB limits feature set expansion
• RAM: 96KB total (64KB + 32KB peripheral) constrains buffer sizes
• Processing: ARM Cortex-M4 @ 120MHz sufficient for current features
• Remote Flash: Memory layout prevents safe over-the-network firmware updates

Current Workarounds

• External Storage: microSD interface for future data logging
• Efficient Protocols: Custom binary formats minimize bandwidth
• Streaming Architecture: Minimal buffering with real-time forwarding

Migration to v2.0

v2.0 architecture addresses v1.x limitations:

• FPGA Processing: Configurable digital signal processing
• Enhanced MCU: Larger memory for complex features
• Remote Updates: Safe over-the-network firmware updates
• Advanced Analytics: On-device machine learning capabilities

Migration Notes

Hardware Migration

• v1.1 → v1.2: Pin configuration changes require firmware updates
• Mechanical compatibility maintained for existing installations
• Enhanced performance available with firmware updates

Firmware Compatibility

• v1.0 ↔ v1.1: Pin-compatible, firmware interchangeable
• v1.1 → v1.2: Requires firmware update for pin changes
• v1.2 → v1.1: Not recommended due to missing backup power monitoring

Development Environment

• Debugging: Tag-Connect interface for SWD debugging
• Build System: MCUXpresso IDE with custom build configurations
• Testing: Hardware-in-the-loop test framework for validation

This document is updated with each hardware revision and firmware release. For the latest version, contact [email protected]