ADR-001: Wave v2 Architecture

Status: Accepted Date: November 2025 Confidential: Internal engineering documentation

Executive Summary

Selected Architecture: Integrated isolated ADC (AMC131M03) with pass-through FPGA

Key Decision Drivers:

• Superior SNR performance: 100 dB vs v1’s 85–90 dB (AMC1350-limited)
• Complete isolation from measurement to network (competitive wedge vs PQube)
• Lower cost: $27 vs $33 current v1 design
• Lower development risk: 8–12 weeks vs 16–20 weeks for modulator+FPGA approach
• IEC 61000–4–30 Class A capable (vs v1’s Class S)

Architecture Overview

Analog Signal → Integrated Isolated ADC → FPGA (pass-through + DSP offload) → MCU → Network
                (AMC131M03)                (Future: harmonic/FFT computation)

Key Principle: Use best-in-class integrated isolated ADC for baseline performance, keep FPGA for future DSP offload and expandability.

Design Evolution

Initial Approach (Considered)

Isolated delta-sigma modulators (Si8935, ISOSD61) + FPGA demodulation for flexibility

Abandoned because:

• All modulators limited to 86 dB SNR (couldn’t beat v1’s ADE9430 target of 101 dB)
• Higher development complexity and risk
• Longer time to IEC 61000–4–30 Class A certification

Current v1 Design (Baseline)

• ADE9430 energy metering IC: 101 dB SNR, 16.5-bit ENOB
• AMC1350 isolated amplifier front-end: $21/unit
• Actual system SNR: 85–90 dB (limited by AMC1350, not ADE9430)
• Total cost: $33 per unit ($21 AMC1350 + $12 ADE9430)
• Limitation: No complete isolation (AMC1350 isolates front-end only)

Note: For potential v1.3 improvements (if interim revision needed before v2 production), see ../wave-v1/todo-mods.md. Most of those improvements are already incorporated into v2 architecture.

Final Decision: AMC131M03

Integrated isolated ADC that matches ADE9430 performance with complete isolation

Component Evaluation

AMC131M03 (Texas Instruments) - SELECTED

Performance:

• SNR: 100 dB @ 4 kSPS (gain = 1)
• ENOB: 16.3 bit typical
• Dynamic Range: 102 dB
• Resolution: 24-bit delta-sigma ADC
• Sample Rate: 1 kSPS to 64 kSPS (per channel)
• Channels: 3 differential per chip
• Programmable Gain: 1×, 2×, 4×, 8×, 16×, 32×, 64×, 128× (independent per channel)
• Isolation: Integrated capacitive barrier, 5 kV rating
• Cost: ~$9 per chip (3 channels), ~$27 for 7-channel system (3 chips)

Oversampling Capability:

• 4 kSPS: 16.3-bit ENOB (baseline)
• 1 kSPS: ~16.8-bit ENOB (4× oversampling)
• 250 SPS: ~17.3-bit ENOB (16× oversampling)
• Each 4× reduction in sample rate: +3 dB SNR ≈ +0.5 bit ENOB

Strengths:

• Matches v1’s target ADE9430 performance (100 dB vs 101 dB, negligible difference)
• Superior to v1’s actual performance (100 dB vs 85–90 dB AMC1350-limited)
• Complete isolation (no separate AMC1350 needed)
• Lower total cost than current v1 design ($27 vs $33)
• Integrated DC/DC converter (shared power architecture)
• Simultaneous sampling across all channels (critical for power quality phase measurement)
• Extensive programmable gain range (more than ADE9430)
• Proven, production-ready component (lower risk)

Limitations:

• Maximum 64 kSPS sample rate (vs 200+ kSPS possible with Si8935 + FPGA)
• Adequate for 99% of power quality applications (IEC 61000–4–30 requires 10.24 kHz minimum)
• Harmonic measurement to 50th harmonic @ 60 Hz (25 kHz bandwidth @ 64 kSPS)

Strategic Value:

• Complete isolation as competitive wedge against PQube (they have no front-end isolation)
• Class A certification path: 100 dB SNR enables IEC 61000–4–30 Class A (vs v1’s Class S)
• Install anywhere: High-voltage panels, VFD-heavy environments, medical-grade applications
• Time-to-market: 8–12 weeks development vs 16–20 weeks for modulator+FPGA approach

Alternative 1: Si8935 + FPGA Demodulation (Considered)

Architecture:

• Isolated delta-sigma modulator (Si8935): 25 MHz bit stream
• FPGA: Custom decimation and filtering algorithms
• Flexible sample rates: 16 kHz to 200+ kHz

Performance:

• SNR: 86 dB typical (14-bit ENOB)
• Input Range: ±2.25V (widest available)
• Cost: ~$3/channel × 7 channels = ~$21 modulators + FPGA + shared DC/DC ≈ $45 total

Abandoned because:

• Lower SNR: 86 dB vs 100 dB (AMC131M03) - can’t beat v1 performance
• Higher development risk: Custom FPGA demodulation algorithms require extensive validation
• Longer certification: More time to prove IEC 61000–4–30 Class A compliance
• Higher cost: $45 vs $27 (67% more expensive)
• Flexibility not needed: 64 kSPS adequate for 99% of applications

Only advantage: Higher sample rates (200+ kHz) for arc flash detection or supraharmonic analysis

• Not compelling for v2 target applications
• Can address in v3 if market demand emerges

Alternative 2: ISOSD61 + FPGA (Considered)

Specifications: 86 dB SNR, 25 Msps, ±320 mV input range

Abandoned for same reasons as Si8935, plus:

• Narrower input range (±320 mV vs ±2.25V) requires higher front-end gain
• Higher front-end gain amplifies noise, negating SNR advantage

Alternative 3: Current v1 Design (ADE9430 + AMC1350)

Cost: $33 per unit
Performance: 85–90 dB system SNR (AMC1350-limited)
Isolation: Front-end only (not complete)

Why v2 with AMC131M03 is better:

• -18% cost: $27 vs $33
• +10–15 dB SNR: 100 dB vs 85–90 dB
• Complete isolation: Measurement to network (competitive advantage)
• Simpler design: Fewer components, easier supply chain

Multi-Channel Architecture

Channel Configuration

• 7 active measurement channels: 3 voltage + 4 current (differential)
• 2 expansion channels: DC voltage/current, temperature, vibration, analog sensors
• 3× AMC131M03 chips (3 channels each = 9 total):
  • Chip 1: V1, V2, V3 (phase voltages at gain = 1)
  • Chip 2: I1, I2, I3 (phase currents at gain = 4)
  • Chip 3: I0, Spare1, Spare2 (neutral current + 2 expansion)

Why grouped channels vs per-phase isolation?

• CT and Rogowski coil sensors output isolated voltage signals
• All current sensors referenced to common ground/neutral (V0)
• No 440V differential between channels (unlike shunt-based designs)
• Per-phase isolation (TI’s automotive reference) only needed for line-potential shunts
• Field power quality monitoring doesn’t use shunts (require breaking conductors, unsafe)

Time Synchronization

• All 3 chips share common clock source (FPGA or MCU generates master clock)
• Simultaneous sampling across all 9 channels
• Critical for accurate V×I power calculation (phase angle precision <0.1°)
• Enables differential measurements (V1-V0, I1-I0, etc.)

Programmable Gain Strategy

Voltage Channels (Gain = 1):

• Maximize SNR: 100 dB
• Input range: ±1.2V full-scale
• Front-end scaling: 600V RMS L-L → ±1.2V peak (voltage divider network)

Current Channels (Gain = 4):

• Balanced SNR: ~95 dB (still excellent, 15.5-bit ENOB)
• Input range: ±300 mV full-scale
• Compatible with CT/Rogowski outputs (typically 100–200 mV @ rated current)

Expansion Channels (Configurable):

• Gain selected based on sensor type (temperature: gain=64, DC voltage: gain=1, etc.)
• Firmware-configurable without hardware changes

SNR vs Gain Trade-off (AMC131M03):

Digital Rogowski Integration

v1 Approach (analog):

• INA851RG analog integrator per current channel
• Cost: $3–5 per channel × 4 = $12–20
• Issues: Temperature drift, RC time constant variations, fixed integration time

v2 Approach (digital):

• Direct Rogowski connection: Coil → RC filter → AMC131M03 @ gain=16–64
• FPGA or MCU performs digital integration: I(t) = Σ(dI/dt × Δt) + high-pass filter
• Advantages:
  • No drift (purely digital, no RC components)
  • Configurable integration time constant (firmware, supports any Rogowski coil)
  • DC offset removal via digital high-pass filter
  • Calibration in software (no trimming)
  • Cost savings: $12–20 per unit
• Computational load: ~10 ops/sample × 4 channels × 32 kHz = 1.3 MOPS (trivial for 150 MHz M33)

Result: Firmware-configurable sensor support without analog circuitry changes

For detailed storage format specification, see onboard-storage-format.md

For FPGA strategy and selection rationale, see ADR-003-wave-v2-fpga-strategy.md

FPGA Role

Selected FPGA: Lattice ECP5–17/25 (144-TQFP, $20–25 @ qty 50)

Key Functions:

• Multi-chip SPI aggregation (3× AMC131M03)
• Digital Rogowski integration
• GPS PPS hardware timestamping (<1 μs precision for IEEE C37.118)
• EtherCAT deterministic control (<100 μs latency)
• Future DSP offload capability (field-upgradable)

Justification: 6% COGS increase unlocks 50–100% larger addressable market by enabling utility synchrophasor and industrial automation applications.

Performance Comparison

Competitive Positioning

vs PQube3 (Primary Competitor)

PQube3 Architecture:

• COGS: ~$900 (estimated)
• Complexity: 7 PCBs, 2 cooling fans, onboard Linux computer (Raspberry Pi), integrated touchscreen
• Size: Large enclosure (DIN rail mounting difficult)
• Installation: Control room only (no front-end isolation)
• Connectivity: Ethernet only (no fiber option)
• Retail price: ~$2500

PQube3 Limitations:

• No front-end isolation (relies on building’s isolation transformers)
• Cannot install in high-voltage panels or VFD enclosures (safety concern)
• Requires significant panel space (large enclosure)
• Complex thermal management (fans required)
• Higher failure rate (many components, moving parts)

EQ Wave v2 Advantages:

System Architecture Comparison:

PQube3 Approach (monolithic):

• All functions in one device: sensor + computer + display + network
• Complex, high COGS, requires control room installation
• Limited scalability (one sensor, one display)

EQ Wave v2 + Syntropy Gateway Approach (distributed):

• Sensor: EQ Wave v2 ($400 COGS) - install anywhere, complete isolation
• Gateway: EQ Syntropy Gateway ($400 COGS, i.MX8M) - optional, far more capable than PQube’s RPi
  • Handles multiple sensors (10–100+ per gateway)
  • Modern Linux stack (Rust binaries)
  • Industrial HMI or cloud connectivity
  • Can license Rust binaries for custom gateway (user’s own hardware)
• Total: $800 for complete system, but gateway amortized across many sensors

Cost advantage at scale:

• 1 sensor + display: PQube3 = $900, EQ = $800 (comparable)
• 10 sensors + centralized monitoring: PQube3 = $9000, EQ = $4000 + $400 gateway = $4400 (51% savings)
• 100 sensors: PQube3 = $90k, EQ = $40k + $400 gateway = $40.4k (55% savings)

Marketing Message: “The only power quality monitor you can safely install directly in high-voltage panels and VFD-heavy environments—complete isolation from measurement to network. And unlike monolithic competitors, our distributed architecture scales effortlessly from 1 to 100+ sensors with a single gateway.”

Unique Value Propositions vs Competitors

1. Install-Anywhere Safety (CRITICAL DIFFERENTIATOR)

• Problem: PQube/Fluke can’t safely install in 600V breaker panels (no/limited isolation)
• Solution: EQ Wave 5 kV complete isolation (measurement → digital → network)
• Impact: Install at measurement point, no 100ft wire runs, electrician-friendly
• Market: Data centers, semiconductor fabs, hospitals (space-constrained, safety-critical)

2. Control-Ready Architecture (NEW PRODUCT CATEGORY)

• Problem: PQube/Fluke are monitoring-only (no real-time control outputs)
• Solution: FPGA + EtherCAT enables <1ms control loops
• Impact: Active harmonic filtering, VAR compensation, motor coordination, arc flash mitigation
• Market: System integrators, automation vendors (+$10k-50k per project for custom algorithms)

3. 2× Sample Rate (PERFORMANCE)

• EQ Wave: 64 kSPS (50th harmonic @ 60 Hz)
• PQube: ~32 kHz (50th harmonic)
• Fluke 1760: 10.24 kHz (50th harmonic, but slower transients)
• Impact: Better transient capture, motor inrush, VFD switching

4. Dual Network Standard (ISOLATION + FLEXIBILITY)

• PQube: RJ45 only (no electrical isolation option)
• Fluke: RJ45 standard, fiber expensive add-on
• EQ Wave: POF + RJ45 both included
• Impact: Complete electrical isolation or convenient copper, customer choice

5. Supercap Backup Standard (RELIABILITY)

• PQube: Unknown (probably not)
• Fluke: Battery backup (hours, but $6k device)
• EQ Wave: 10-sec supercap (captures events, no battery replacement)
• Impact: Never miss voltage sags/interruptions (IEC 61000–4–30 compliance)

6. Software Licensing (BUSINESS MODEL)

• PQube/Fluke: Fixed feature set
• EQ Wave: Tiered licensing (Energy → PQ → Control)
• Impact: Lower entry price ($1500), upsell path (+$300–800), services revenue

For detailed pricing strategy and business model, see pricing-and-business-model.md

IEC 61000–4–30 Certification Path

Class A Requirements (AMC131M03 Capable)

• Voltage accuracy: ±0.1% (AMC131M03 supports this with 16.3-bit ENOB)
• Current accuracy: ±0.5% (easily achieved with 15.5-bit ENOB @ gain=4)
• Frequency accuracy: ±0.01 Hz (MCU calculation, not ADC-limited)
• Harmonic measurement: Up to 50th harmonic (25 kHz @ 64 kSPS—sufficient)
• Phase accuracy: ±0.1° (simultaneous sampling critical—AMC131M03 provides this)

Class S (v1 Baseline)

• Voltage: ±1%, Current: ±2%, Harmonics to 25th
• ADE9430 limited to Class S despite 16.5-bit ENOB due to non-isolated architecture

Development Timeline

• Prototype validation: 4 weeks (AMC131M03 SPI interface, basic data acquisition)
• Power quality algorithms: 4–6 weeks (RMS, THD, harmonics, flicker)
• Class A certification testing: 4–6 weeks (independent lab, IEC compliance)
• Total: 8–12 weeks (vs 2–3 weeks for ADE9430 integration, but far superior product)

Bill of Materials Comparison

ADC Subsystem Cost Analysis

Cost Summary:

• v1 to v2 savings: $21 per unit (base) to $37 per unit (with optional AC PSU savings)
• v2 (AMC131M03) vs v2 (Si8935): $27 cheaper, better performance, lower risk

Full System COGS Estimate

Based on actual v1.2 production ($420 per unit @ qty 11):

• v1 measured cost: $480 per unit including enclosure ($420 + $60 enclosure/final assembly)

v2 estimated COGS @ qty 50:

At production volume (qty 1000+):

• FPGA cost drops: $20 → $12–15 (-$5–8)
• Assembly cost drops: $120 → $60–80 (-$40–60)
• PCB cost drops: $30 → $15–20 (-$10–15)
• Estimated COGS @ qty 1000: $280–320

Optional AC Power Supply Board

• Component cost: $12 (AC/DC converter module + passives)
• Assembly: $5 (plug-in module, minimal labor)
• Total: $17 per unit
• Strategy: Field-installable, order only if needed (reduces base unit cost)

Risk Assessment

AMC131M03 Approach (Selected)

Technical Risk: Low

• Production-proven component (TI standard product)
• SPI interface well-documented
• Reference designs available
• No custom analog design (integrated front-end)

Schedule Risk: Low

• 8–12 weeks development (straightforward SPI integration)
• FPGA used as pass-through (minimal complexity)
• Power quality algorithms standard (FFT, RMS, THD)

Supply Chain Risk: Low

• Texas Instruments (tier-1 supplier)
• Standard product (not EOL risk)
• Multi-sourcing possible (similar AMC131 family members)

Performance Risk: Low

• Meets IEC 61000–4–30 Class A requirements
• 64 kSPS adequate for all target applications
• Proven SNR performance (100 dB typical)

Si8935 + FPGA Approach (Rejected)

Technical Risk: Medium-High

• Custom FPGA demodulation algorithms
• Decimation filter design (sinc + FIR compensation)
• Group delay characterization
• Temperature stability validation

Schedule Risk: Medium

• 16–20 weeks development (FPGA algorithm development)
• Higher iteration cycles for validation
• More complex Class A certification (prove FPGA filtering)

Performance Risk: Medium

• SNR limited to 86 dB (can’t beat v1 target)
• FPGA filtering must compensate for modulator limitations
• Temperature drift management in FPGA

Decision Summary

Architecture: 3× AMC131M03 integrated isolated ADC + Lattice ECP5 FPGA (pass-through) + MCXN947 dual-core MCU

Channel Configuration:

• Chip 1: V1, V2, V3 (phase voltages @ gain=1, 100 dB SNR)
• Chip 2: I1, I2, I3 (phase currents @ gain=4, 95 dB SNR)
• Chip 3: I0, Spare1, Spare2 (neutral + 2 expansion for DC/temp/vibration)

Key Decision Drivers:

1. Best available performance: 100 dB SNR matches v1 ADE9430 target, beats v1 actual (85–90 dB AMC1350-limited)
2. Complete isolation: Competitive wedge against PQube ($900 COGS, no isolation), medical-grade safety
3. Lower cost: $37 savings per unit vs v1 (ADC: -$47, Rogowski: -$16, AC PSU: -$17, MCU: +$2.50, FPGA: +$20, front-end: -$5)
4. Lower risk: Production-proven component (TI), straightforward SPI integration, 8–12 weeks development
5. Class A capable: IEC 61000–4–30 Class A certification path (vs v1’s Class S)
6. Superior PGA: 1–128× gain per channel (more extensive than ADE9430), firmware-configurable
7. Digital Rogowski integration: No analog integrators (INA851RG), firmware-configurable for any coil
8. Time synchronization: Simultaneous sampling across all 9 channels, critical for phase angle precision
9. Expansion channels: 2 spare channels for DC, temperature, vibration, pressure (firmware-selectable)
10. Simplified BOM: 3× identical chips, streamlined supply chain

Cost Analysis:

• v1 COGS: $480 per unit @ qty 11 (actual production data)
• v2 COGS: $405 per unit @ qty 50 (estimated, including testing/firmware)
• v2 COGS @ qty 1000: $280–320 (production volume)
• vs PQube3: 2.25× lower COGS ($400 vs $900), scales better (distributed architecture)

Trade-offs Accepted:

• Maximum 64 kSPS sample rate (vs 200+ kSPS with Si8935 + FPGA)
  • Adequate for 99% of applications (IEC 61000–4–30 requires 10.24 kHz minimum)
  • 50th harmonic @ 60 Hz = 3 kHz → 64 kSPS provides 21× oversampling
  • Arc flash detection still < 16 μs response time
• No supraharmonic analysis (2–150 kHz range)
  • Market demand unclear (niche applications)
  • Can address in v3 if needed
• No shunt current measurement at line potential
  • Field power quality monitoring uses CT/Rogowski (isolated sensors)
  • Shunts impractical (require breaking conductors, safety concerns)
  • Low-current DC shunt measurement still possible via expansion channels

Strategic Advantages:

• Install anywhere: High-voltage panels, VFD enclosures, medical facilities (5 kV isolation)
• Distributed architecture: Multiple sensors + single gateway (scales 10–100+ sensors)
• Firmware-upgradable: FPGA DSP offload in future firmware (FFT, harmonics)
• Expandable platform: Add DC monitoring, temperature, vibration without hardware changes
• No moving parts: Passive cooling (aluminum enclosure), higher reliability than PQube (fans)

Future Expansion Path:

• Phase 1 (v2.0): FPGA pass-through, MCU does all DSP
• Phase 2 (v2.1+): Migrate FFT/harmonic computation to FPGA (field-upgradable)
• Phase 3 (v3.0, 2027–2028): Technology roadmap for supraharmonic capability

v3 Technology Roadmap (2027–2028)

If supraharmonic analysis demand emerges (2–150 kHz bandwidth), v3 will have better options:

Likely Option A: Next-Gen Integrated Isolated ADC

• AMC131M04/M05 (TI’s 2-year product cycle predicts 2026 announcement)
• Target specs: 100 dB SNR @ 128–256 kSPS (vs v2’s 64 kSPS)
• Same architecture, just faster sampling
• Lowest risk path: Proven architecture, direct drop-in upgrade
• Cost: $10–15 per chip (similar to current pricing structure)

Option B: Improved Isolated Modulators + FPGA

• Next-gen modulators: 90–95 dB SNR, 30–40 MHz bit rate (vs today’s 86 dB, 25 MHz)
• Still won’t beat integrated ADC baseline performance
• Only pursue if supraharmonics require >256 kSPS

Technology prediction timeline:

• 2026: TI announces AMC131M04 or equivalent (128 kSPS integrated isolated ADC)
• 2027: Production availability, early adopter designs
• 2028: v3 design window opens with mature component availability

Decision for v2: AMC131M03 @ 64 kSPS is the best available technology today. By 2027–2028, much better options will exist if supraharmonic market demand materializes. No reason to compromise v2 with inferior modulators while waiting for future technology.

For detailed mechanical design, see mechanical-design.md and expansion-options.md

Enclosure: 90mm W × 110mm L × 36mm D aluminum extrusion with CNC end caps

Expansion Architecture: 2 slots (side-by-side), main board + optional expansion cards (AC/DC power, GPS/EtherCAT communications, or gateway SOM)

Key Features: Side-accessible SD card, snap-in LED indicators, flex cable expansion, double-sided 6-layer PCB

Implementation Plan

Phase 1 (Q4 2025 - Current): Design lock and integration testing

• Final schematic and layout validation (~86×106mm main board, 6-layer, double-sided SMT)
  • 3× AMC131M03 + MCXN947 + ECP5 + GPS + EtherCAT (all populated on early units)
  • Component placement optimization validated (thermal clearances confirmed)
  • SD card on lengthwise side, LEDs with snap-in lens, RJ45 on main board
• AC/DC power board design finalized (2-layer, field-installable via flex cable)
• Communication expansion board design finalized (GPS + EtherCAT, field-installable via flex cable)
• Flex cable specifications: Board-to-board connectors, signal routing for GPS/EtherCAT/FPGA GPIO
• Enclosure design locked: 90×110×36mm extruded profile, CNC end caps with side access slots
  • Multi-card expansion architecture validated (stacked cards via flex cable)
  • Connector layout finalized (voltage top, current/network bottom, SD/LEDs on side)
• BOM locked for prototype run
• FPGA integration tests (SPI communication, timing validation)
• Deliverable: Design files ready for prototype fabrication

Phase 2 (Jan–Feb 2026): Alpha prototypes and firmware integration

• Alpha board assembly (v2.0 prototypes, 5–10 units)
• FPGA firmware development:
  • SPI master to 3× AMC131M03 (9 channels @ 32 kHz baseline)
  • Digital Rogowski integration (real-time)
  • GPS PPS hardware latching (< 1 μs precision)
  • Event trigger logic (voltage sag/swell, overcurrent)
• MCU firmware:
  • Core 1: Network stack (dual interface, TCP servers for PMon/CPOW/config)
  • Core 2: Power quality algorithms (FFT, RMS, THD, harmonics, flicker)
• Gateway integration (Zenoh protocol, configuration management)
• Bench testing with programmable AC source (Chroma or California Instruments)
• Deliverable: Functional alpha units with basic PQ algorithms and gateway integration

Phase 3 (Mar–Apr 2026): Beta deployment and certification prep

• Beta units to named pilot customers (10–15 units):
  • Hitachi Energy (utility substation validation)
  • Advantiv (industrial EMI immunity, VFD environments)
  • Texas Instruments (semiconductor fab precision validation)
• Field testing in diverse environments:
  • High-EMI industrial (VFD immunity)
  • Clean room / semiconductor (precision and accuracy)
  • Utility substation (IEC 61000–4–30 Class A validation)
• Pre-compliance testing (EMC, safety, isolation)
• Algorithm refinement based on field data
• Documentation development (user manual, installation guide, API reference)
• Deliverable: Field-validated beta units, certification test plan

Phase 4 (May–Jul 2026): Limited production and certification

• Production design locked (incorporate beta feedback)
• Initial production run (≤100 units)
• UL/FCC/CE certification submission
  • UL 61010–1 (safety, isolation)
  • FCC Part 15 Class B (EMI emissions)
  • IEC 61000–4–30 Class A (accuracy)
• Early customer shipments (existing pilot customers + new orders)
• Field support infrastructure setup
• Deliverable: Certified production v2.0

Phase 5 (Q4 2026): Full production readiness

• Manufacturing optimization (yield improvement, cost reduction)
• General availability announcement
• Expanded distribution and sales channels
• v2.1 firmware planning: FPGA DSP offload (FFT/harmonic computation)
• SKU optimization (separate GPS/EtherCAT vs base units based on demand data)
• Deliverable: Production-ready supply chain, market rollout

Phase 6 (2027): Scale-up and advanced features

• Production scaling (500–1000 units/year capacity)
• Manufacturing partner transition: Switch from MacroFab to Keytronic once cumulative volume exceeds 500 units and design is stable
  • MacroFab: Prototype through low-volume production (<500 units total)
  • Keytronic: High-volume production partner (>500 units, stable design)
  • Benefits: Lower per-unit assembly costs, better volume pricing, dedicated production line
  • Timing: Transition after design proven stable (minimal ECOs), order backlog justifies volume commitment
• v2.1 firmware release: FPGA-accelerated FFT/harmonics
• Expanded AI feature set:
  • FPGA DSP offload for edge analytics
  • PMU synchronization (IEEE C37.118)
  • Supraharmonic monitoring (2–150 kHz, experimental)
• Expansion channel applications (DC monitoring, temperature, vibration)
• Control Edition customer deployments

Document Status: Final architecture decision, approved for v2 development
Last Updated: January 2025
Next Review: After alpha prototype validation (Feb 2026)